VHDL Tutorial: T Flip-Flop using Behavioral Modeling

2 Comments

  • Sir,if u wouldn't have used 's' ie,logic in the above program then how it would afffect the program.Instead of assigning 's' variable ,why u haven't used 'q' itself that acts as output?

  • sir,here if reset=1 then s is assigned to 0 then why are we not getting 0 as output for reset condition.Since it asynchronous reset, it is not dependent on clock whatever the s value assigned in reset state should come as output.

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