Microwind Implementation of D Flip Flop Using TRANSMISSION GATES

In this tutorial we are going to implement D Flip Flop For which we are going to implement this digram We will require here two 2:1 MUX The first one and the second as shown And we will use 4 inverters This bubble here is the first inverter this is the second Same is replicated here again. The third and fourth Inverter We are not going to create all the elements again, We can use Previously created one simply by copying I have created here a 2:1mux and a inverters logically the 2:1 mux created here is same as we did in previous video . its connections are changed in a manner suitable for our design We are going to use the replica of these components to implement this circuit So we are going to copy the whole circuit so far created Lets use the copy tool available here let me align this we have to connect the output of mux to input of inverter and feed back the output of inverter again to mux at its first input. As you can see I named all the terminals of mux as ,clk,clkbar this is output lets connect this output to input of inverter . we are implementing this part only And final output here i.e. of second inverter is to be fed back to mux lets connect here like this We completed the implementation of this half of circuit we connected clock and clock bar signals to s and sbar terminals of mux 0 input of mux is named as d input of flipflop which has very high frequency than clock so it will toggle at faster rate than clock and clock bar As a result it will be easier to verify operation in simulation. the same output that we fed back is to be connected to first terminal of second mux i.e. here we will connect clock and clock bar of first mux only . no need for these signals here as shown in the circuit diagram Again connect the output of mux to input of first inverter and output of 1st inverter to 2nd inverter And fed final output back to 0 input of second mux this is the final output connect it to 0 input of mux lets connect clock and clock bar now At any point if you make any mistake you can use undo function by ctrl+u shortcut lets extend this in this manner now we are done with circuit implementation wherever possible we will short n-well, vdd and vss terminals we can not short vss here due to complex comnnections so leave it lets short both n-wells and vdd here lets place output node to make output visible in simulation let us check the circuit with help of simulation As we can see here the D input is delayed by whole clock cycle and is available at Q output we can check the delay of 1 clockcycle everywhere it is fine not simulating clock bar for verification purpose do so by deselecting this “visible in simulation ” option here So it becomes easier to verify the result verification of result again after removal of clockbar from simulation If you find my videos helpful please do like, share and subscribe


  • good job 🙂

  • Bhava khup madat jhali tuzi .. thank you

  • Thanks brother it helps me a lot 🙂

  • thaknx bhawa……
    punyacha ahes ka?

  • sir, I m doing my project using microwind, I didnt find 45 nm in which I have been using ..but I seen 45 nm technology in ur video.. so plzzz mail me microwind folder which will b useful for my project..

  • can i get the file

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