Lecture 31: Latches and Flip-Flops (Part I)


  • Sir in Gated SR latch using NAND Gates
    if E=0 You said it doesn't matter what the value of S and R is(Don't care)-Output will not change
    but when E=0 S'=R'=1 which is invalid combination and the output will depend on the speed of the gates(race around condition)
    that means the stored element will either be a 0 or 1 (Q=0,Q'=1 or Q=1,Q'=0)
    but in the state table you mentioned No change. Why ?

  • Tq sir it helped me

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