D Flip Flops

>>Good day, this is Jim Pytel from Columbia George
Community College. This is Digital Electronics. This lecture’s entitled
D-Flip Flops. We’re going to take the
edge detection device which we’ve previously discussed
and add it to the front of some previously
discussed devices and see how it modifies
its behavior. If you remember,
the gated SR Latch, one of our basic
sequential devices — how we created D Latch to that
is all we did was took this D input, fed it to S, inverted
it, fed it to R, put it in a box and call it a D Latch, okay? What’s the behavior
of a D Latch? My description of it is Q
follows D when it’s enabled. When it’s not enabled, Q
takes the last value of D. So, let’s see if we can
modify D Latch with an edge detection device
by doing the exact same thing, taking an edge detection
device, in this case, it’s positive edge detection
device, put it on the front of enable, put it in a box and
call that box a D Flip Flop. So now it’s kind
of the same thing. It follows D when enabled. Well, it’s only enabled
for a brief moment of time. If you could think about it, it’s almost like it’s
sampling D, okay? Let’s take a quick look at it and that quick momentary look
is instantaneous sampling. And that’s the way I like
to describe a D Flip Flop in contrast to a D Latch. Q samples D when it’s enabled. It stores that value
until it’s enabled again. The thing is, is you have to
remember is when is it enabled? In this particular case, it
is a positive edge there. What if I had a bubble
in front of that, it would be enabled
on a negative edge? And this idea of a sample
versus follow a D Latch when it’s enabled
that enable pulse. Say for example, it’s
active high enable. It’s enabled for
50 microseconds. It’s taking that D.
It’s following it, that whole 50 microseconds
as opposed to a positive edge
detection device, it samples on that brief moment
in time on the positive edge in this particular case
of a clock [inaudible]. Let’s go ahead and
just try some examples, and again you use
this description. You should remember
these descriptions. How does an SR Latch work? How does a D Latch work? How does a D Flip Flop work? Just think of the
behavior of these things. Okay, here’s our first example. We’ve got a D Flip Flop. Is it a positive edge detection
of a negative edge detection? To me this looks like it’s a
positive edge detection device. What is my initial conditions? What I’m saying is this
Q’s initially a zero. How do I do it timing
analysis of this? Exact same way I’ve done
the SR Latch and D Latch. I figure out when it’s —
when is this thing enabled? It’s enabled on the
positive edge. All you do is just find
where the positive edges are. Okay, so there’s all
the positive edges. And what is the behavior
of D Flip Flop? It samples D when it’s enabled. So, I’ll just draw lines
down, sampling it right there, right there, right
there and actually where I should be drawing on
that one, what’s it sampling? It’s sampling a one there, okay? So just figure out
where it’s sampling and it should look like this. Those are all the times of
its sampling that input. And then, what does Q do? It’s basically assuming those
values when it is sampled. So, you just go along. It’s a zero. It’s a zero. It’s going to stay
a zero until here. It’s a one sampling
a one, and it’s going to stay a one even though
that that D is changed there. It will stay a one until
it samples a zero again. You’ve already figured
this out too. Q to some of these
analyses is just kind of using a straight edge. You could potentially take
a ruler with you to class. You could potentially
use a piece of paper as the straight edges
kind of figure out when these things
are enabled in this particular example with some positive
edge detection device. Okay, how would this behave if it was a negative edge
detection device, namely Q? How would Q change
as a result of that? Here’s another follow-up
question? How would this change
if it was a D Latch, let’s that it was
active high enabled? How would it change if it was
an active low enabled D Latch? Okay, so we’re using a
bunch of terminologies which all sound very
similar, but your key to differentiate those
things, that Q is going to behave differently
for every single one of those descriptions. So let’s try another
example here. We have a D signal and a
clock signal and we’ve got Q in this particular example. It’s an unknown state. How do we make this thing work? Well, we figure out
okay, when is it in it? I’m looking at the clock signal. Looks like it’s got the
description called a positive edge detection device on it. So I figure out when
it’s enabled. There you go. Those are the only
times that it’s enabled and those positive edges of the
clock, not the positive edges of D; that is a number
one misconception of people doing these. It’s a positive edges on the
signal reaching the clock input. And now, how does Q respond? I know there’s some
unknown state. We don’t know what’s Q
— what’s in Q up until, it could be a zero,
it could be a one, but kind of at this point, we don’t care what it
was, because it’s a one. And it’s going to stay a one until it’s sampled again
right there, which is a zero, and it’s going to stay a
zero until it’s sampled again which happens to be
a zero and it’s going to stay a zero despite the
fact that D is moving now, because it’s not sampled
again right there. And it’s going to stay a
one until it’s sampled again which happens to be
a one and it’s going to stay a one despite the fact that D is falling
down to a zero. And at that point,
it’s sampled again. That becomes a zero. Follow-up question,
how this behaves if it was a negative
edge detection device? And there is some
problems in there with a negative edge detection
device which we’ll discuss in one of the follow-along
lectures regarding Flip Flop Operating Characteristics. But how would this behavior if
it was an active high D Latch where the clock was being sent
to the active high enable? How would it behave if it
was an active low D Latch? Let’s do another example of
this same type of problem. When it is enabled, the
negative edge detection device, what is the behavior
of a D Flip Flop? It samples D when
enabled, stores that value. Okay, when is it enabled? It’s enabled on negative edge. Okay, there’s all
the negative edges. It’s sampling it here, there,
there, there, there, there. What is my initial
conditions for Q? I’m saying it was a one
when we first started. Regardless of what D is,
it’s going to stay a one until it’s sampled at that
moment which is a one, and it’s going to stay
a one despite the fact that D is changing until
it’s sampled again here, which is a zero, zero and
it’s going to stay that way until it’s sampled again
at a one despite the fact that D is changing right there. It was up right there,
samples again. It’s a one and it’s going to
stay a one despite the fact that D is changing right here until it samples D
again which is a zero. Same question, how
would this behave if it was an active
high D Latch? How would it behave if it
was an active low D Latch? How would it behave if it was
a positive edge detection D Flip Flop? Okay, so there’s a number of different example
problems you can get from the same problem. So that should’ve been
pretty easy understanding of D Flip Flops. What I’m going to
do is introduce to you now is this concept
of A synchronous inputs. Okay, so D, it is a
synchronous input. Why is it a synchronous input? Because the only time
you ever look at D is with respect to the clock. The clock is synchronizing
the activity. There is such a thing
called asynchronous inputs. Asynchronous inputs are things
that supersede the clock. They can be looked at regardless
wherever the clock is. And what I’m going to do is just
give you a basic description of asynchronous input and
just see how you do with it. Don’t even worry how these
things are hooked up right now. Just think of this, there
are — This is a D Flip Flop. Pay no attention
to the other stuff which I’ve drawn
on it right now. What is it? Well, here is a D input. Here is a positive edge on it, a
positive edge detection device. It’s a D Flip Flop. Here’s a Q output, and you
also have the not-Q output if you want to use
it for some reason. Those two things that
I’ve drawn there, those two additional
things are what is known as asynchronous inputs,
meaning those things can be read without respect to the clock,
and the supersede what’s ever on the clock and the two inputs
what I’m calling is not PRE and not CLR. Don’t call them that. They’re called preset and CLR. Okay, preset. What that means — what is set? It’s a one, okay? So if I’m presetting something, I’m basically loading
everything with a one. What is a CLR? Well just think about it. It is the empty mind Zen state. There’s zero in there, CLR. I’m clearing the thing out. What is the purpose of
these sequential devices? One of the major functions of sequential device
is a memory device. Say for example, I have a
register which is a storage. Maybe it would be a good idea
is prior to using that register, I should clear the whole thing out so there’s no
garbage in them. Maybe I want to load the
whole thing with ones. I’m going to preset it. This bar over it and the bar
over it — What that means? Well it’s active low. Grab your head. Squeeze from both side, because
I don’t want it to explode. Okay, well what is
active low mean? It means it’s looking for zero. So if the preset input
has a zero on it, it will load all ones to Q.
If clear has a zero on it, it’s going to clear Q. It’s
going to put a zero on Q and because they are
asynchronous, you don’t have to look at the clock, and
because they’re asynchronous, they supersede inputs
based on the clock. That probably hit you like
a ton of bricks right there, because we haven’t really
talked about asynchronous. This is the first time
I’m introducing it. But, let’s just try a
timing diagram of this. One of the key things
to remember about these timing diagrams,
and I still haven’t even put D and PRE and CLR on there. It’s just think about
the behavior. When does the input D — when
is the input D being looked at? It’s being looked at,
at the positive edge. When is the input PRE being
looked at, the preset input? When is the CLR being looked at? These guys are being looked
at all the time regardless of what D is doing or
the clock is doing. If there’s a zero on CLR
regardless of what’s going on — Let’s say there’s a zero right
there for CLR, all the rest of the times, it’s high, what
do you think Q is going to be? It’s going to be CLR. So let’s put some inputs on D.
Let’s put some inputs on preset and let’s put an input on CLR. So I’ve got D incoming data. I’ve got PRE active low preset. I’ve got CLR and active low CLR. And remember preset and
CLR are asynchronous. You do not have to worry about
the clock with those inputs. But how do I do a problem
with this — like this. Well step one, what
type of device is this? Well it’s a D Flip Flop with a
positive edge detection device. Figure out where the
positive edges are. Step two, figure out what the
initial conditions for Q are. Well it’s zero. Step three, when
does it sample D? Right there, right there,
right there, right there, right there and right there. Step zero — step zero,
basically before all that garbage there,
look at this, PRE and CLR, they’re
asynchronous. Don’t worry about the clock. Whatever the clock is
doing, whatever D is doing, if there’s a low on
PRE, it will preset it. It will put a one on Q.
If there’s a low on CLR, it will put a zero on Q. And
it’s going to stay that way until the next time
the device is enabled. So let’s just look at CLR. When is it zero? Right there. So basically, it’s
going to stay a zero until the next time it’s
sampled, right there. So that whole time,
Q should be a zero at which time it’s
enabled and sampled. Don’t worry about that right
now, because we’re still dealing with the presets and CLRs. Look at CLR again. There’s a zero there. It’s active low. It’s asynchronous inputs
regardless of what’s going on. From this point forward,
Q should be a zero. What happens with preset? It’s active low, asynchronous. At this moment right there,
regardless of what Q is doing, it’s going to put a one on Q,
and it’s going to stay that way until it’s sampled again. So what I’m doing is forget all
the clocks, forget all the Ds. Before you do anything, look
at the presets and the CLRs. They’re active low
asynchronous inputs. Now, go ahead and do
step one through three. Here’s where my positive edges. There they are. They’ve sampled it. At that particular time, it’s
being sampled right here again. It is a zero and it will stay a
zero until it’s sampled again. So it’s going to go along right
about here, changes up to a one, goes along until it’s sampled
again right about there, and it’s going to stay a one. Then it just so happens to
be a one when it’s preset, at which point it’s
sampled again, which is a zero right there,
and it’s going to stay a zero until it is sampled again at
a zero, and it just so happens to have that CLR at that time. Getting those presets and CLRs
before even doing the timing analysis is absolutely
important to this. And again, this is an
added functionality to this device here. Let’s say for example I’ve got
this in a register application or a counter that I want
to reset to state zero. All I do is just get every
single device hooked up on that thing and active low CLR
clears the whole thing out and I can use it again. Okay, let’s go on to discuss
the next sequential audit device with an edge detection
device, the JK Flip Flop.


  • Great lectures,very simple explanation.Thanks a lot.Greetings from Turkey

  • I feel like; an ultra mega super intelligent robot teaching me with his one tone voice..:-)…thanx for everything

  • Strange voice… Uh. Almost can't concentrate while listening

  • Beautiful!!

  • Your voice makes me feel drowsy

  • your voice is very clear and your lesson comprehensible.I take this lesson in my university but I didn't understand in my language.thanks from turkey

  • Brilliant, Absolutely brilliant. Thanks and keep it up!! 🙂

  • Strange voice but cool keep going 😀 Video helped me a lot, thx

  • this was excellent.. thank you

  • what happens when clear and preset and both equal to 0?

  • The voice is great.

  • Outstanding way of teaching, analogies are great! keep up the good work sir!!

  • thank you bro…i wish all professors can explain as you do

  • Wanted to let you all know I'm currently developing content for another YouTube channel at:


    The "Basic Electronics 1: DC Circuit Analysis" playlist will be finished summer 2015 and I've posted sample content for other playlists. This channel is undergoing major development and is regularly updated. Subscribe to it if you're interesting in getting the latest content. Long terms plans include a complete basic electronics series (DC, AC, 3 phase AC), motor control, power electronics, motors and generators, hydraulics, renewable energy, and more! Enjoy!

  • Hey Jim, you R very good on this field man, I really appreciate your time and effort.

  • thank you very much. I have a test of it tomorrow, and now i just understand how it works

  • Hey Jim, I want to thank you for this video. You really helped me out today. Great explanation. Keep it up!

  • Brilliant explanation Jim ! Bec of your explanation of D and JK flip flops. I aced my exam .. Thank you very much my friend …

  • This guy is a genius…great explanations.

  • omg thank you. i hate taking this class in hs because teachers dont really care

  • thank you

  • GREAT video. Thank you !

  • Never talked about the D Latch…..

  • thank you!

  • Explained in 13 minutes what my professor couldn't in 45 minutes of lecture. Thank you!

  • Mr Jim Pytel, next time you have an argument with someone, just record your point of view using this exact mic and send it to him. 11/10

  • thanks for your effort

  • I can't find an in-depth explanation for what D and Q are, at least not in lamon terms. Anyone can lend a hand?

  • Very clear. Your videos are excellent. I only wish I had found them earlier. There's a lot of people watching these vids – perhaps more should click like.

  • How do I determine the initial condition for Q ?

  • you saved my ass

  • I can't with the vocal fry

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