D-Flip Flop using Xilinx 8.1 ISE (With Subs)

Yup ..Back again ….. OOPS I prefer to keep clock as first..And I’ll let you know why This is a sequential circuit We will be having Q and Qb… which are both outputs and inputs Why Qb?? Well its short for Q bar….. DONT ASK Pause the video if you want the code I’ll put it in the comments too I purposely made an error here…So please watch the full video first Green tick !! Yay!! D….e..t..e..s..t..e..r Notice how the first variable is the default clock set here…… No one said you can’t manually design the clock But I felt this is easier Set D to whatever..Do not have to bother with Q and Qb ………….Yup…………..
Done Now lets get output Did you remember me telling about an error? That’s the error We’ll go back to the code page Now what we are going to do is…. You are free to write Q as 1 and Qb as 0 But make sure they are complimentary Now we gotta create another test file Thats the change ..So remember it !!!! We delete the old file and make a new test file Same clk as clock Change d as you want Leave Q and Qb as they are SIMULATE! Woohoo As you can see Q is following D as clock is rising and Qb is going against Q and D So thats about it So yeah…All the best !! Sambit signing off

One Comment



    if rising_edge(clk) then



    end if;

    end process;

Leave a Comment

Your email address will not be published. Required fields are marked *